Instruction: Add two signed values plus C.

ADDSX SValue1, < # > SValue2

Result: Sum of signed SValue1 and signed SValue2 plus C flag is stored in SValue1.

SValue1 (d-field) is the register containing the value to add to SValue2 plus C, and is the destination in which to write the result.
SValue2 (s-field) is a register or a 9-bit literal whose value plus C is added into SValue1.

Opcode Table:

–INSTR– ZCRI –CON– –DEST– –SRC–	Z Result	C Result	Result	Clocks
110110 001i 1111 ddddddddd sssssssss	Z & (D+S+C = 0)	Signed Overflow	Written	4

Concise Truth Table:

In					Out
Destination	Source	Z	C	Effects	Destination	Z	C
$FFFF_FFFE; -2	$0000_0001; 1	x	0	wz wc	$FFFF_FFFF; -1	0	0
$FFFF_FFFE; -2	$0000_0001; 1	0	1	wz wc	$0000_0000; 0	0	0
$FFFF_FFFE; -2	$0000_0001; 1	1	1	wz wc	$0000_0000; 0	1	0
$0000_0001; 1	$FFFF_FFFE; -2	x	0	wz wc	$FFFF_FFFF; -1	0	0
$0000_0001; 1	$FFFF_FFFE; -2	0	1	wz wc	$0000_0000; 0	0	0
$0000_0001; 1	$FFFF_FFFE; -2	1	1	wz wc	$0000_0000; 0	1	0
$7FFF_FFFE; 2,147,483,646	$0000_0001; 1	x	0	wz wc	$7FFF_FFFF; 2,147,483,647	0	0
$7FFF_FFFE; 2,147,483,646	$0000_0001; 1	x	1	wz wc	$8000_0000; -2,147,483,648	0	1
$7FFF_FFFE; 2,147,483,646	$0000_0002; 2	x	0	wz wc	$8000_0000; -2,147,483,648	0	1
$8000_0001; -2,147,483,647	$FFFF_FFFF; -1	x	0	wz wc	$8000_0000; -2,147,483,648	0	0
$8000_0001; -2,147,483,647	$FFFF_FFFE; -2	x	0	wz wc	$7FFF_FFFF; 2,147,483,647	0	1
$8000_0001; -2,147,483,647	$FFFF_FFFE; -2	x	1	wz wc	$8000_0000; -2,147,483,648	0	0

Explanation

ADDSX (Add Signed, Extended) sums the two signed values of SValue1 and SValue2 plus C, and stores the result into the SValue1 register. The ADDSX instruction is used to perform signed multi-long addition; 64-bit additions, for example.

In a signed multi-long operation, the first instruction is unsigned (ex: ADD), any middle instructions are unsigned, extended (ex: ADDX), and the last instruction is signed, extended (ex: ADDSX). Make sure to use the WC, and optionally WZ, effect on the leading ADD and ADDX instructions.

For example, a signed double-long (64-bit) addition may look like this:

add     XLow,    YLow   wc   wz      'Add low longs together; save C and Z
addsx   XHigh,   YHigh               'Add high longs together

After executing the above, the double-long (64-bit) result is in the long registers XHigh:XLow. If XHigh:XLow started out as $0000_0001:0000_0000 (4,294,967,296) and YHigh:YLow was $FFFF_FFFF:FFFF_FFFF (-1) the result in XHigh:XLow would be $0000_0000:FFFF_FFFF (4,294,967,295). This is demonstrated below.

                         Hexadecimal             Decimal
                      (high)     (low) 
  (XHigh:XLow)      $0000_0001:0000_0000      4,294,967,296
+ (YHigh:YLow)    + $FFFF_FFFF:FFFF_FFFF    +            -1
                  ----------------------    ---------------
                  = $0000_0000:FFFF_FFFF    = 4,294,967,295

A signed triple-long (96-bit) addition would look similar but with an ADDX instruction inserted between the ADD and ADDSX instructions:

add      XLow,     YLow     wc    wz    'Add low longs; save C and Z
addx     XMid,     YMid     wc    wz    'Add middle longs; save C and Z
addsx    XHigh,    YHigh                'Add high longs

Of course, it may be necessary to specify the WC and WZ effects on the final instruction, ADDSX, in order to watch for a result of zero or signed overflow condition. Note that during this multi-step operation the Z flag always indicates if the result is turning out to be zero, but the C flag indicates unsigned carries until the final instruction, ADDSX, in which it indicates signed overflow.

For ADDSX, if the WZ effect is specified, the Z flag is set (1) if Z was previously set and SValue1 + SValue2 + C equals zero (use WC and WZ on preceding ADD and ADDX instructions). If the WC effect is specified, the C flag is set (1) if the summation resulted in a signed overflow. The result is written to SValue1 unless the NR effect is specified.