Instruction: Pause a cog's execution temporarily.

WAITCNT Target, < # > Delta

Result: Target + Delta is stored in Target.

Target (d-field) is the register with the target value to compare against the System Counter (CNT). When the System Counter has reached Target's value, Delta is added to Target and execution continues at the next instruction.
Delta (s-field) is the register or a 9-bit literal whose value is added to Target's value in preparation for the next WAITCNT instruction. This creates a synchronized delay window.

Opcode Table:

–INSTR– ZCRI –CON– –DEST– –SRC–	Z Result	C Result	Result	Clocks
111110 001i 1111 ddddddddd sssssssss	Result = 0	Unsigned Carry	Written	6+

Concise Truth Table:

In					Out
Destination	Source	Z	C	Effects	Destination	Z	C
$0000_0000; 0	$0000_0000; 0	-	-	wz wc	$0000_0000; 0	1	0
$FFFF_FFFF; 4,294,967,295	$0000_0001; 1	-	-	wz wc	$0000_0000; 0	1	1
$0000_0000; 0	$0000_0001; 1	-	-	wz wc	$0000_0001; 1	0	0

Explanation

WAITCNT, "Wait for System Counter," is one of four wait instructions (WAITCNT, WAITPEQ, WAITPNE, and WAITVID) used to pause execution of a cog until a condition is met. The WAITCNT instruction pauses the cog until the global System Counter equals the value in the Target register, then it adds Delta to Target and execution continues at the next instruction. The WAITCNT instruction behaves similar to Spin's WAITCNT command for Synchronized Delays; see WAITCNT.

If the WZ effect is specified, the Z flag will be set (1) if the sum of Target and Delta is zero. If the WC effect is specified, the C flag will be set (1) if the sum of Target and Delta resulted in a 32-bit carry (overflow). The result will be written to Target unless the NR effect is specified.