Instruction: Pause a cog's execution until I/O pin(s) match designated state(s).

WAITPEQ State, < # > Mask

State (d-field) is the register with the target state(s) to compare against INx ANDed with Mask.
Mask (s-field) is the register or a 9-bit literal whose value is bitwise ANDed with INx before the comparison with State.

Opcode Table:

–INSTR– ZCRI –CON– –DEST– –SRC–	Z Result	C Result	Result	Clocks
111100 000i 1111 ddddddddd sssssssss	—	—	Not Written	6+

Concise Truth Table:

In					Out
Destination	Source	Z	C	Effects	Destination¹	Z	C
$0000_0000; 0	$0000_0000; 0	-	-	wr wz wc	$0000_0000; 0	1	0
$0000_0000; 0	$0000_0001; 1	-	-	wr wz wc	$0000_0001; 1	0	0
$0000_0001; 1	$0000_0001; 1	-	-	wr wz wc	$0000_0002; 2	0	0
$0000_0000; 0	$0000_0002; 2	-	-	wr wz wc	$0000_0002; 2	0	0
$0000_0002; 2	$0000_0002; 2	-	-	wr wz wc	$0000_0004; 4	0	0

¹ Destination is not written unless the WR effect is given.

Explanation

WAITPEQ, "Wait for Pin(s) to Equal," is one of four wait instructions (WAITCNT, WAITPEQ, WAITPNE, and WAITVID) used to pause execution of a cog until a condition is met. The WAITPEQ instruction pauses the cog until the result of INx ANDed with Mask equals the value in the State register. INx is either INA or INB depending on the value of the C flag upon execution; INA if C = 0, INB if C = 1 (the P8X32A is an exception to this rule; it always tests INA).

The WAITPEQ instruction behaves similar to Spin's WAITPEQ command; see WAITPEQ.

mov vcfg, VscCfg
VscCfg long %000000000000_10100000_101000000000