Opcodes and Opcode Tables

Most syntax definitions include an opcode table similar to the one below. This table lists the instruction's 32-bit opcode, outputs and number of clock cycles.

The opcode table's first column contains the Propeller Assembly Instruction opcode, consisting of the following fields:

INSTR (bits 31:26)	Indicates the instruction being executed.
ZCRI (bits 25:22)	Indicates instruction's effect status and SRC field meaning.
CON (bits 21:18)	Indicates the condition in which to execute the instruction.
DEST (bits 17:9)	Contains the destination register address.
SRC (bits 8:0)	Contains the source register address or 9-bit literal value.

The bits of the ZCRI field each contain a 1 or 0 to indicate whether or not the 'Z' flag, 'C' flag, and 'R'esult should be written, and whether or not the SRC field contains an 'I'mmediate value (rather than a register address). The Z and C bits of the ZCRI field are clear (0) by default and are set (1) if the instruction was specified with a WZ and/or WC effect. See Effects (WC, WZ, WR, NR). The R bit's default state depends on the type of instruction, but is also affected if the instruction was specified with the WR or NR effect. The I field's default state depends on the type of instruction and is affected by the inclusion, or lack of, the literal indicator (#) in the instruction's source field.

The bits of the CON field usually default to all ones (1111) but are affected if the instruction was specified with a condition. See IF_x (Conditions).

The last four columns of the opcode table indicate the meaning of the instruction's output Z and C flags, the default behavior for writing or not writing the result value, and the number of clocks the instruction requires for execution.

CLKSET Opcode Table:

–INSTR– ZCRI –CON– –DEST– –SRC–	Z Result	C Result	Result	Clocks
000011 0001 1111 ddddddddd ------000	—	—	Not Written	8..23