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Registers

Register(s)

Description

DIRA, DIRB3

Direction Registers for 32-bit port A and 32-bit port B, see DIRA, DIRB0DIRB and DIRA, DIRB. The optional "[Pin(s)]" parameter does not apply to Propeller Assembly; all bits of the entire register are read/written at once, unless using the MUXx instructions.

INA1, INB1,3

Input Registers for 32-bit port A and 32-bit port B (Read-Only), see INA, INB0INB and INA, INB. The optional "[Pin(s)]" parameter does not apply to Propeller Assembly; all bits of the entire register are read at once.

OUTA, OUTB3

Output Registers for 32-bit port A and 32-bit port B, see OUTA, OUTB0OUTB and OUTA, OUTB.
The optional "[Pin(s)]" parameter does not apply to Propeller Assembly; all bits of the entire register are read/written at once, unless using the MUXx instructions.

CNT1

32-bit System Counter Register (Read-Only), see CNT0 CNT and CNT.

CTRA, CTRB

Counter A and Counter B Control Registers, see CTRA, CTRB0CTRB and CTRA, CTRB.

FRQA, FRQB

Counter A and Counter B Frequency Registers, see FRQA, FRQB0FRQB and FRQA, FRQB.

PHSA2,PHSB2

Counter A and Counter B Phase-Locked Loop Registers, see PHSA, PHSB0PHSB and PHSA, PHSB.

VCFG

Video Configuration Register, see VCFG0 VCFG and VCFG.

VSCL

Video Scale Register, see VSCL0 VSCL and VSCL.

PAR1

Cog Boot Parameter Register (Read Only), see PAR0 PAR and PAR.

Note 1: For Propeller Assembly, only accessible as a source register (i.e., mov dest, source). See the Assembly language sections for PAR, CNT, and INA, INB.
Note 2: For Propeller Assembly, only readable as a source register (i.e., mov dest, source); read modify-write not possible as a destination register. See the Assembly language section for PHSA, PHSB.
Note 3: Reserved for future use.