CLK Register
The CLK register is the System Clock configuration control; it determines the source of and the characteristics for the System Clock. More precisely, the CLK register configures the RC Oscillator, Clock PLL, Crystal Oscillator, and Clock Selector circuits. (See Figure 1 2: Propeller Chip Block Diagram on page .) It is configured at compile time by the _CLKMODE constant (page ) and is writable at run time through the CLKSET Spin command (page ) or the CLKSET assembly instruction (page ). Whenever the CLK register is written, a global delay of ≈75 µs occurs as the clock source transitions.
Whenever this register is changed, a copy of the value written should be placed in the Clock Mode value location (which is BYTE[4] in Main RAM) and the resulting master clock frequency should be written to the Clock Frequency value location (which is LONG[0] in Main RAM) so that objects which reference this data will have current information for their timing calculations. (See CLKMODE, page , and CLKFREQ, page .) When possible, it is recommended to use Spin's CLKSET command (page ), since it automatically updates all the above-mentioned locations with the proper information.
Only certain bit patterns in the CLK register are valid clock modes. See the _CLKMODE constant on page and Table 2 4 on page for more information. The Clock object in the Propeller Library may also be useful since it provides clock modification and timing methods.
Table 1 5: CLK Register Structure |
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Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Name |
RESET |
PLLENA |
OSCENA |
OSCM1 |
OSCM0 |
CLKSEL2 |
CLKSEL1 |
CLKSEL0 |
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Table 1 6: CLK Register RESET (Bit 7) |
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Bit |
Effect |
0 |
Always write '0' here unless you intend to reset the chip. |
1 |
Same as a hardware reset – reboots the chip. The Spin command REBOOT writes a '1' to the RESET bit. |
Table 1 7: CLK Register PLLENA (Bit 6) |
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|---|---|
Bit |
Effect |
0 |
Disables the PLL circuit. The RCFAST and RCSLOW settings of the _CLKMODE declaration configure PLLENA this way. |
1 |
Enables the PLL circuit. Each of the PLLxx settings of the _CLKMODE declaration configures PLLENA this way at compile time. The Clock PLL internally multiplies the XIN pin frequency by 16. OSCENA must also be '1' to propagate the XIN signal to the Clock PLL. The Clock PLL's internal frequency must be kept within 64 MHz to 128 MHz – this translates to an XIN frequency range of 4 MHz to 8 MHz. Allow 100 µs for the Clock PLL to stabilize before switching to one of its outputs via the CLKSELx bits. Once the Crystal Oscillator and Clock PLL circuits are enabled and stabilized, you can switch freely among all clock sources by changing the CLKSELx bits. |
Table 1 8: CLK Register OSCENA (Bit 5) |
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|---|---|
Bit |
Effect |
0 |
Disables the Crystal Oscillator circuit. The RCFAST and RCSLOW settings of the _CLKMODE declaration configure OSCENA this way. |
1 |
Enables the Crystal Oscillator circuit so that a clock signal can be input to XIN, or so that XIN and XOUT can function together as a feedback oscillator. The XINPUT and XTALx settings of the _CLKMODE declaration configure OSCENA this way. The OSCMx bits select the operating mode of the Crystal Oscillator circuit. Note that no external resistors or capacitors are required for crystals and resonators. Allow a crystal or resonator 10 ms to stabilize before switching to a Crystal Oscillator or Clock PLL output via the CLKSELx bits. When enabling the Crystal Oscillator circuit, the Clock PLL may be enabled at the same time so that they can share the stabilization period. |
Table 1 9: CLK Register OSCMx (Bits 4:3) |
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OSCMx |
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_CLKMODE Setting |
XOUT Resistance |
XIN/XOUT Capacitance |
Frequency Range |
1 |
0 |
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0 |
0 |
XINPUT |
Infinite |
6 pF (pad only) |
DC to 80 MHz Input |
0 |
1 |
XTAL1 |
2000 Ω |
36 pF |
4 to 16 MHz Crystal/Resonator |
1 |
0 |
XTAL2 |
1000 Ω |
26 pF |
8 to 32 MHz Crystal/Resonator |
1 |
1 |
XTAL3 |
500 Ω |
16 pF |
20 to 60 MHz Crystal/Resonator |
Table 1 10: CLK Register CLKSELx (Bits 2:0) |
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CLKSELx |
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_CLKMODE Setting |
Master Clock |
Source |
Notes |
2 |
1 |
0 |
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0 |
0 |
0 |
RCFAST |
~12 MHz |
Internal |
No external parts. |
0 |
0 |
1 |
RCSLOW |
~20 kHz |
Internal |
Very low power. No external parts. |
0 |
1 |
0 |
XINPUT |
XIN |
OSC |
OSCENA must be '1'. |
0 |
1 |
1 |
XTALx and PLL1X |
XIN x 1 |
OSC+PLL |
OSCENA and PLLENA must be '1'. |
1 |
0 |
0 |
XTALx and PLL2X |
XIN x 2 |
OSC+PLL |
OSCENA and PLLENA must be '1'. |
1 |
0 |
1 |
XTALx and PLL4X |
XIN x 4 |
OSC+PLL |
OSCENA and PLLENA must be '1'. |
1 |
1 |
0 |
XTALx and PLL8X |
XIN x 8 |
OSC+PLL |
OSCENA and PLLENA must be '1'. |
1 |
1 |
1 |
XTALx and PLL16X |
XIN x 16 |
OSC+PLL |
OSCENA and PLLENA must be '1'. |
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