Register: Video Scale Register.
((PUB ┆ PRI))
VSCL
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Returns: Current value of cog's Video Scale Register, if used as a source variable.
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Explanation
VSCL is one of two registers (VCFG and VSCL) that affect the behavior of a cog's Video Generator. Each cog has a video generator module that facilitates transmitting video image data at a constant rate. The VSCL register sets the rate at which video data is generated.
VSCL Register |
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VSCL Bits |
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31..20 | 19..12 | 11..0 | ||||
− | PixelClocks | FrameClocks |
PixelClocks
The 8-bit PixelClocks field indicates the number of clocks per pixel; the number of clocks that should elapse before each pixel is shifted out by the video generator module. These clocks are the PLLA clocks, not the System Clock.
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The 12-bit FrameClocks field indicates the number of clocks per frame; the number of clocks that should elapse before each frame is shifted out by the video generator module. These clocks are the PLLA clocks, not the System Clock. A frame is one long of pixel data (delivered via the WAITVID command). Since the pixel data is either 16 bits by 2 bits, or 32 bits by 1 bit (meaning 16 pixels wide with 4 colors, or 32 pixels wide with 2 colors, respectively), the FrameClocks is typically 16 or 32 times that of the PixelClocks value.
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Using VSCL
VSCL can be read/written like other registers or pre-defined variables. For example:
Code Block |
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VSCL := %000000000000_10100000_101000000000 |
This sets the video scale register for 160 PixelClocks and 2,560 FrameClocks (for a 16-pixel by 2-bit color frame). Of course, the actual rate at which pixels clock out depends on the frequency of PLLA in combination with this scale factor.