Register: Special Purpose Register array; provides indirect access to cog's special registers.
((PUB ┆ PRI))
SPR [Index]
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Returns: Value in special purpose register at Index.
- Index is an expression that specifies the index (0-15) of the special purpose register to access (PAR through VSCL).
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Explanation
SPR is an array of the 16 special purpose registers in the cog. Element 0 is the PAR register and element 15 is the VSCL register. See Table 2 15 the Cog RAM Special Purpose Registers table below. SPR provides an indirect method of accessing the cog's special purpose registers.
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Cog RAM Special Purpose Registers |
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Name | Index | Type | Description | ||||||
PAR | 0 | Read-Only | Boot Parameter | ||||||
CNT | 1 | Read-Only | System Counter | ||||||
INA | 2 | Read-Only | Input States for P31 - P0 | ||||||
INB | 3 | Read-Only | Input States for P63- P321 | ||||||
OUTA | 4 | Read/Write | Output States for P31 - P0 | ||||||
OUTB | 5 | Read/Write | Output States for P63 – P321 | ||||||
DIRA | 6 | Read/Write | Direction States for P31 - P0 | ||||||
DIRB | 7 | Read/Write | Direction States for P63 - P321 | ||||||
CTRA | 8 | Read/Write | Counter A Control | ||||||
CTRB | 9 | Read/Write | Counter B Control | ||||||
FRQA | 10 | Read/Write | Counter A Frequency | ||||||
FRQB | 11 | Read/Write | Counter B Frequency | ||||||
PHSA | 12 | Read/Write | Counter A Phase | ||||||
PHSB | 13 | Read/Write | Counter B Phase | ||||||
VCFG | 14 | Read/Write | Video Configuration | ||||||
VSCL | 15 | Read/Write | Video Scale | ||||||
~subscript~1 1Reserved for future use|
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Using SPR
SPR can be used like any other long-sized array. The following assumes Temp is a variable defined elsewhere.
| Code Block |
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spr[4] := %11001010 'Set outa register |
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Temp := spr[2] 'Get ina value |
This example sets the OUTA register (index 4 of SPR) to %11001010 and then sets Temp equal to the INA register (index 2 of SPR).